1. Field of Endeavor
Exemplary embodiments of the present disclosure generally relate to an apparatus for simplification of input signal.
2. Background
The information disclosed in this Discussion of the Related Art section is only for enhancement of understanding of the general background of the present disclosure and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Generally, a high speed counter module of PLC (Programmable Logic Controller) is a module configured to function to count a fast pulse signal of a pulse generator or an encoder that cannot be counted by a general counter command.
FIG. 1 is a block diagram illustrating a configuration of a PLC high speed counter according to prior art.
Referring to FIG. 1, an input circuit (20) converts a high speed pulse signal generated by an encoder (10) to CMOS level signal for transmission to an outside interrupt port of an MPU (Micro Processor Unit, 30). The MPU (30) adds, deducts or disregards without any operation, a current value in response to a pulse input mode of the encoder (10) when a signal of the outside interrupt port connected to the input circuit (20) rises or falls, i.e., at a rising edge or a falling edge.
FIG. 2 is a block diagram illustrating an input circuit (20) of a PLC high speed counter according to prior art.
Referring to FIG. 2, signals of A-phase and B-phase of encoder (10) from outside connector is converted to a CMOS signal, which is in turn transmitted to A-phase and B-phase outside interrupt ports of MPU (30).
FIGS. 3a and 3f are schematic views illustrating six different input modes and operations thereof according to types of encoder (10). Hereinafter, a first mode refers to 1-phase/2-input/1-multiplication mode, a second mode refers to 1-phase/2-input/2-multiplication mode, a third mode refers to CW (Clockwise)/CCW (Counterclockwise) mode, a fourth mode refers to 2-phase/1-multiplication, a fifth mode refers to 2-phase/2-multiplication, and a sixth mode refers to 2-phase/4-multiplication, for convenience sake. The detailed operation of the first to sixth modes will be explained later.
FIG. 4 is a flow chart illustrating a flow of processing an interrupt according to prior art when the interrupt is generated in an outside interrupt ports of MPU (30) in the PLC high speed counter. FIG. 4a illustrates a case where an interrupt is generated on A phase, and FIG. 4b illustrates a case where an interrupt is generated on B phase.
Referring to FIGS. 4a and 4b, when an interrupt is generated on A phase, the MPU (30) operates in a method of determining by repeating at every time at which mode among first to sixth modes the interrupt is generated. Furthermore, when an interrupt is generated on B phase, the MPU (30) operates in a method of determining by repeating at every time at which mode between third mode and sixth mode the interrupt is generated. Thus, when an interrupt is generated, the MPU (30) determines by repeating at every time to what mode an input mode corresponds.
Meantime, the MPU (30) temporarily stops the PLC scan program whenever a rising edge or a falling edge of an input signal connected to an outside interrupt port is detected, and performs a high speed counter processing routine after the interrupt is generated. Thus, when an edge of an input mode is detected according to the prior art, an interrupt processing time is lengthened in response to the performance of process shown in FIGS. 4a and 4b according to the input mode, and when a speed of input pulse string (train) increases, the resources of MPU is excessively and disadvantageously occupied due to delay in interrupt processing. Another disadvantage as a result thereof is that the processing speed of PLC scan program is slowed.